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*# Implementing a memory barrier
*# Performing an [[Atomic Operation]]
*#* '''Atomics''' are operations which must be completed in a single step (or appear to be completed in a single step) without potential interruption.
*#* Wikipedia has a good basic overview of the need for atomicity in the article on [http://en.wikipedia.org/wiki/Linearizability Linerarizability]
*# Gaining performance (by accessing processor features not exposed by the high-level language being used (C, C++, ...))
* [[SPO600 Inline Assembler Lab|Inline Assembler Lab]] (Lab 7)
=== Week 6 Deliverables ===
* Blog your Lab 7 results.
== Week 7 ==
=== Week 7 - Class I ===
==== Overview/Review of Processor Operation ====
* Fetch-decode-dispatch cycle
* Pipelining
* Branch Prediction
* In-order vs. Out-of-order execution
** Micro-ops
==== Memory Basics ====
* Organization of Memory
* Memory Speeds
* Cache
** Cache lookup
** Cache synchronization and invalidation
** Cache line size
* Prefetch
** Prefetch hinting
==== Memory Architecture ====
* Virtual Memory and Memory Management Units (MMUs)
** General principles of VM and operation of MMUs
** Memory protection
*** Unmapped Regions
*** Write Protection
*** Execute Protection
*** Privilege Levels
** Swapping
** Text sharing
** Data sharing
** Copy-on-Write (CoW)
** Demand Loading
==== Memory Barriers ====
'''Memory Barriers''' ensure that memory accesses are sequenced so that multiple threads, processes, cores, or IO devices see a predictable view of memory.
* Leif Lindholm provides an excellent explanation of memory barriers.
** Blog series - I recommend this series, especially the introduction, as a very clear explanation of memory barrier issues.
*** Part 1 - [http://community.arm.com/groups/processors/blog/2011/03/22/memory-access-ordering--an-introduction Memory Access Ordering - An Introduction]
*** Part 2 - [http://community.arm.com/groups/processors/blog/2011/04/11/memory-access-ordering-part-2--barriers-and-the-linux-kernel Memory Access Ordering Part 2 - Barriers and the Linux Kernel]
*** Part 3 - [http://community.arm.com/groups/processors/blog/2011/10/19/memory-access-ordering-part-3--memory-access-ordering-in-the-arm-architecture Memory Access Ordering Part 3 - Memory Access Ordering in the ARM Architecture]
** Presentation at Embedded Linux Conference 2010 (Note: Acquire/Release in C++11 and ARMv8 aarch64 appeared after this presentation):
*** [http://elinux.org/images/f/fa/Software_implications_memory_systems.pdf Slides]
*** [http://free-electrons.com/pub/video/2010/elce/elce2010-lindholm-memory-450p.webm Video]
* [http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.07.23a.pdf Memory Barriers - A Hardware View for Software Hackers] - This is a highly-rated paper that explains memory barrier issues - as the title suggests, it is designed to describe the hardware origin of the problem to software developers. Despite the fact that it is an introduction to the topic, it is still very technical.
* [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka14041.html ARM Technical Support Knowlege Article - In what situations might I need to insert memory barrier instructions?] - Note that there are some additional mechanisms present in ARMv8 aarch64, including Acquire/Release.
* [https://www.kernel.org/doc/Documentation/memory-barriers.txt Kernel Documentation on Memory Barriers] - discusses the memory barrier issue generally, and the solutions used within the Linux kernel. This is part of the kernel documentation.
* Acquire-Release mechanisms
** [http://blogs.msdn.com/b/oldnewthing/archive/2008/10/03/8969397.aspx MSDN Blog Post] with a very clear explanation of Acquire-Release.
** [http://preshing.com/20130922/acquire-and-release-fences/ Preshing on Programming post] with a good explanation.
** [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.genc010197a/index.html ARMv8 Instruction Set Architecture Manual] (ARM InfoCentre registration required) - See the section on Acquire/Release and Load/Store, especially Load/Store Exclusive (e.g., LDREX)
=== Week 7 - Class II ===
* Course Project
=== Week 7 Deliverables ===
* Blog your Lab 7 results, including the second part
* (To be announced: Project Deliverables)
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== Week 3 ==