The Armv9 Scalable Vector Extensions verision 2 (SVE2) provide a variable-witdh SIMD capability for AArch64 systems.
- Arm Armv9-A A64 Instruction Set Architecture - https://developer.arm.com/documentation/ddi0602/2021-12/
- Introduction to SVE2 - https://developer.arm.com/documentation/102340/0001/?lang=en
- Intrinsics - Arm C Language Extensions for SVE (ACLE) - https://developer.arm.com/documentation/100987/latest
- SVE Coding Considerations with Arm Compiler - Note that this documentation is specific to Arm's own compiler, but most of it will be applicable to other compilers including gcc - https://developer.arm.com/documentation/100748/0616/SVE-Coding-Considerations-with-Arm-Compiler
Building SVE2 Code
C Compiler Options
To build code that includes SVE2 instructions, you will need to instruct the complier or assembler to emit code for an Armv8a processor that also understands the SVE2 instructions; this is performed using the
-march= option (which is read as "machine architecture"). You must do this regardless of whether you're using autovectorization, inline assembler, or intrinsics. The architecture specificaion for this target is currently "armv8-a+sve2":
gcc -march=armv8-a+sve2 ...
Remember that in order to invoke the autovectorizer in GCC version 11, you must use
-O3 or the appropriate feature options (
gcc -O3 -march=armv8-a+sve2 ... gcc -O2 -march=armv8-a+sve2 -ftree-vectorize ...
Using SVE2 Intrinsics Header Files
To use SVE2 intrinsics in a C program, include the header file
Note: some ARM documentation will refer to
<arm_sve2.h>, but in gcc, the correct file is
Running SVE2 Code
To run SVE2 code on an Armv8 system, you can use the QEMU usermode system. This will trap SVE2 instructions and emulate them in software, while executing Armv8a instructions directly on the hardware: