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→Week 5 - Class I
*** eight 16-bit lanes
*** sixteen 8-bit lanes
** Each architecture has a different notation for SIMD dataregisters. In AArch64 (which will be our focus):
*** Vector usage uses the notation v''n''.''s'' where ''n'' is the register number and ''s'' is the shape of the lanes, expressed as the number of lanes and a letter indicating the width of the lanes: q for quad-word (128 bits), d for double-word (64 bits), s for single-word (32 bits), h for half-word (16 bits), and b for byte (8 bits). Therefore, <code>v0.16b</code> is vector register 0 used as 16 lanes of 8 bits (1 byte) each, while <code>v8.4s</code> is vector register 8 used as 4 lanes of 32 bits each. Most instructions permit either 64 or 128 bits of the register to be used.
*** Scalar usage uses the lane width followed by the vector register number. Therefore, <code>q3</code> refers to vector register 3 used as a single 128-bit value, and <code>s3</code> refers to the same register used as a single 32-bit register. When using less than 128 bits, the remaining bits are either zero-filled (unsigned usage) or sign-extended (signed usage: the upper bits are filled with the sign bit, i.e., the same value as the high bit of the active part of the register).
