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[[Category:Fall 2019 SPO600]]
This is the schedule and main index page for the [[SPO600]] ''Software Portability and Optimization'' course for Fall 2019.
<!-- {{Admon/important|It's Alive!|This [[SPO600]] weekly schedule will be updated as the course proceeds - dates and content are subject to change. The cells in the summary table will be linked to relevant resources and labs as the course progresses.}}-->
<!-- {{Admon/important|Content being Updated|This page is in the process of being updated from a previous semester's content. It is not yet updated for Fall 2019. Do not rely on the accuracy of this information until this warning is removed.}} -->
== Schedule Summary Table ==
|-
|2||Sep 9||[[#Week 2 - Class I|Intro to Assembler / Using Makefiles]]||[[#Week 2 - Class II|Assembler Lab (Lab 3)]]||[[#Week 2 Deliverables|Blog your conclusion to Labs 1 and 2, and blog about your initial work on Lab 3, and set up Slack access.]]
|-
|-
|4||Sep 23||[[#Week 4 - Class I|Computer Resources and Performance Binary Representation of Data / Baseline Builds Data Type Selection / Benchmarking and ProfilingAlgorithm Selection]]||[[#Week 4 - Class II|Software Build Lab Algorithm Selection (Lab 4)]]||[[#Week 4 Deliverables|Blog your Lab lab 4 results.]]
|-
|5||Sep 30||[[#Week 5 - Class I|Binary Representation of DataSIMD and Vectorization / Inline Assembler]]||[[#Week 5 - Class II|Algorithm Selection SIMD Lab]] (Lab 5) / Inline Assembler]]||[[#Week 5 Deliverables|Blog your lab 5 results.]]
|-
|6||Oct 7||[[#Week 6 - Class I|SIMD Compiler Optimizations / Computer Resources and Vectorization Performance / Inline AssemblerBenchmarking and Profiling]]||[[#Week 6 - Class II|Investigation: Inline Assembler]] SIMD Lab (Continued) (Lab 65)]]||[[#Week 6 Deliverables|Blog your lab 6 Lab 5 results.]]
|-
|7||Oct 14||[[#Week 7 - Class I|Building Software / Projects!]]||[[#Week 7 - Class II|Project selection]]||[[#Week 7 Deliverables|Catch up on any missed labs, blog about your project selection progress.]]
|-
|-
|8||Oct 28||[[#Week 8 - Class I|Intrinsics and SIMDMemory Ordering / Barriers / Acquire-Release Semantics]]||[[#Week 8 - Class II|Project Hacking]]||[[#Week 8 Deliverables|Blog blog about your project.]]
|-
|-
|10||Nov 11||[[#Week 10 - Class I|Memory Ordering / Barriers / Acquire-Release SemanticsIntrinsics]]||[[#Week 10 - Class II|Project Hacking]]||[[#Week 10 Deliverables|Blog about your project.]]
|-
!Category!!Percentage!!Evaluation Dates
|-
|Communication||align="right"|20%||September (Oct 2 - 5%), October (November 10 - 5%), November (Dec 1, 5%), end of course (Dec 13, 5%).
|-
|Quizzes||align="right"|10%||May be held during any class, usually at the start of class. A minimum of 5 one-page quizzes will be given. No make-up/retake option is offered if you miss a quiz. Lowest 3 scores will not be counted. Students with Test Centre accommodations may choose to write the quizzes in the class, or alternately write a monthly quiz in the Test Center.
|Labs||align="right"|10%||See deliverables column above. All labs must be submitted by the end of the course, but it is best if you stay on top of the labs and submit according to the table above.
|-
|Project work||align="right"|60%||3 stages: 15% (Nov 18), 20% (Nov 22Dec 1), 25% (Dec 1113).
|}
## Optional (strongly recommended): [[SPO600 Host Setup|Set up a personal Linux system]].
## Optional: Purchase an AArch64 development board (such as a [http://96boards.org 96Boards] HiKey or Raspberry Pi 3 or 4. (If you use a Pi, install a 64-bit Linux operating system on it, not a 32-bit version).
# Complete [[SPO600 Compiled C Code Review Lab|Lab 1]] and write it up on your blog.
== Week 2 ==
=== Week 2 - Class I ===
* [[Make and Makefiles]]
* [[Assembly Language]]
* [[SPO600 Assembler Lab|Assembler Lab]] (Lab 43)
=== Week 2 - Class II ===
* [[SPO600 Assembler Lab|Assembler Lab]] (Lab 43)
=== Week 2 Deliverables ===
* Blog your results and conclusion to [[SPO600 Code Review Lab|Code Review Lab (Lab 1)]] and [[SPO600 Compiled C Lab|Compiled C Lab (Lab 2)]]
* Blog about your initial work on [[SPO600 Assembler Lab|Lab 3]].
* Set up your account on the [[SPO600_Communication_Tools#Slack|Seneca Open Source Slack Workspace]].
== Week 3 ==
=== Week 3 - Class I ===
* ''Sysadmin for Devs''
** In-class discussion of tips and tricks for efficient work on a Linux server
=== Week 3 - Class II ===
* Finish [[SPO600 Assembler Lab|Lab 3]]
=== Week 3 - Deliverables ===
* Finish and blog your detailed results for the [[SPO600 Assembler Lab|Assembler Lab]] (Lab 3)
== Week 4 ==
=== Week 4 - Class I ===
* Binary Representation of Data
** Integers
*** Integers are the basic building block of binary numbers.
*** In an unsigned integer, the bits are numbered from right to left starting at 0, and the value of each bit is <code>2<sup>bit</sup></code>. The value represented is the sum of each bit multiplied by its corresponding bit value. The range of an unsigned integer is <code>0:2<sup>bits</sup>-1</code> where bits is the number of bits in the unsigned integer.
*** Signed integers are generally stored in twos-complement format, where the highest bit is used as a sign bit. If that bit is set, the value represented is <code>-(!value)-1</code> where ! is the NOT operation (each bit gets flipped from 0→1 and 1→2)
** Fixed-point
*** A fixed-point value is encoded the same as an integer, except that some of the bits are fractional -- they're considered to be to the right of the "binary point" (binary version of "decimal point" - or more generically, the ''radix point''). For example, binary 000001.00 is decimal 1.0, and 000001.11 is decimal 1.75.
*** An alternative to fixed-point values is integer values in a smaller unit of measurement. For example, some accounting software may use integer values representing cents. For input and display purposes, dollar and cent values are converted to/from cent values.
** Floating-point
*** Floating point numbers have three parts: a ''sign bit'' (0 for positive, 1 for negative), a ''mantissa'' or ''significand'', and an ''exponent''. The value is interpreted as <code>''sign'' mantissa * 2<sup>exponent</sup></code>.
** Sound
** Graphics
** Compression techniques
*** Huffman encoding / Adaptive arithmetic encoding
*** Repeated sequence encoding (1D, 2D, 3D)
*** Decomposition
*** Pallettization
*** Psychoacoustic and psychovisual compression
* Problem: Scaling Sound
** Naive approach
** Lookup table
** Fixed-point multiply and shift
=== Week 4 - Class II ===
* [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]] (Lab 4)
=== Week 4 Deliverables ===
* Blog your results to [[SPO600 Algorithm Selection Lab|Lab 4]]
== Week 5 ==
=== Week 5 - Class I ===
* SIMD
** SIMD is an acronym for "Single Instruction, Multiple Data", and refers to a class of instructions which perform the same operation on several separate pieces of data in parallel. SIMD instructions also include related instructions to set up data for SIMD processing, and to summarize results.
** SIMD is based on very wide registers (128 bits to 2048 bits on implementations current as of 2019), and these wide registers can be treated as multiple "lanes" of similar data. These SIMD registers, also called vector registers, can therefore be thought of as small arrays of values.
** A 128-bit SIMD register can be used as:
*** two 64-bit lanes
*** four 32-bit lanes
*** eight 16-bit lanes
*** sixteen 8-bit lanes
** Each architecture has a different notation for SIMD registers. In AArch64 (which will be our focus):
*** Vector usage uses the notation v''n''.''s'' where ''n'' is the register number and ''s'' is the shape of the lanes, expressed as the number of lanes and a letter indicating the width of the lanes: q for quad-word (128 bits), d for double-word (64 bits), s for single-word (32 bits), h for half-word (16 bits), and b for byte (8 bits). Therefore, <code>v0.16b</code> is vector register 0 used as 16 lanes of 8 bits (1 byte) each, while <code>v8.4s</code> is vector register 8 used as 4 lanes of 32 bits each. Most instructions permit either 64 or 128 bits of the register to be used.
*** Scalar usage uses the lane width letter followed by the vector register number. Therefore, <code>q3</code> refers to vector register 3 used as a single 128-bit value, and <code>s3</code> refers to the same register used as a single 32-bit register. Note that these are the same register referred to as v3 for vector usage. When using less than 128 bits, the remaining bits are either zero-filled (unsigned usage) or sign-extended (signed usage: the upper bits are filled with the sign bit, i.e., the same value as the high bit of the active part of the register).
** Most SIMD operations work on corresponding lanes of the operand registers. For example, the AArch64 instruction <code>add v0.8h, v1.8h, v2.8h</code> will take the value in the first lane of register 1, add the value in the first lane of register 2, and place the result in the first lane of register 0. At the same time, the other lanes are processed in the same way, resulting in 8 simultaneous addition operations being performed.
** A small number of SIMD operations work across lanes, e.g., to find the lowest or highest value in all of the lanes, to add the lanes together, or to duplicate a single value into all of the lanes of a register. These are usually used to set up or summarize the results of SIMD operations -- for example, a value of 0 might be duplicated into all of the lanes of a result register, then a loop applied to sum array data into the results register, and then a lane-summing operation performed to merge the results from all of the lanes.
* SIMD capabilities can be used in a program in one of three different ways:
*# The compiler's ''auto-vectorizer'' can be used to identify sections of code to which SIMD is applicable, and SIMD code will automatically be generated.
*#* This works for the basic SIMD operations, but may not be applicable to advanced SIMD instructions, which don't clearly map to C statements.
*#* The compiler will be very cautious about vectorizing code. See the Resources section below for insight into these challenges.
*#** In order to vectorize a loop, among other things, the number of loop iterations needs to be known before the loop starts, memory layout must meet SIMD alignment requirements, loops must not overlap in a way that is affected by vectorization.
*#** The compiler will also calculate a cost for the vectorization: in the case of a small loop, the extra setup before the loop and processing after the loop may negate the benefits of vectorization.
*#* Vectorization in applied by default only at the -O3 level in most compilers. In GCC:
*#** The main individual feature flag to turn on vectorization is <code>-ftree-vectorize</code> (enabled by default at -O3, disabled at other levels).
*#** You can see all of the vectorization decisions using <code>-fopt-info-vec-all</code> or you can see just the missed vectorizations using <code>-fopt-info-vec-missed</code> (which is usually what you want to focus on, because it show only the loops where vectorization was ''not'' enabled, and the reason that it was not). This approach is generally very portable.
*# We can explicitly include SIMD instructions in a C program by using [[Inline Assembly Language|Inline Assembler]]. This is obviously architecture-specific, so it is important to use C preprocessor directives to include/exclude this code depending on the platform for which it is compiled, and to use a generic C implementation on any platform for which you are not providing an inline assembler version.
*# ''C Intrinsics'' are function-like extensions to the C language. Although they look like functions, they are compiled inline, and they are used to provide access to features which are not provided by the C language itself. There is a group of intrinsics which provide access to SIMD instructions. However, the benefit of using these over inline assembler is debatable. SIMD intrinsics are not portable, and should be included with C preprocessor directives like inline assembler.
=== Week 5 - Class II ===
* [[SPO600 SIMD Lab]] (Lab 5)
=== Week 5 Resources ===
==== Auto-vectorization ====
* [https://gcc.gnu.org/projects/tree-ssa/vectorization.html Auto-Vectorization in GCC] - Main project page for the GCC auto-vectorizer.
* [http://locklessinc.com/articles/vectorize/ Auto-vectorization with gcc 4.7] - An excellent discussion of the capabilities and limitations of the GCC auto-vectorizer, intrinsics for providing hints to GCC, and other code pattern changes that can improve results. Note that there has been some improvement in the auto-vectorizer since this article was written. '''This article is strongly recommended.'''
* [https://software.intel.com/sites/default/files/8c/a9/CompilerAutovectorizationGuide.pdf Intel (Auto)Vectorization Tutorial] - this deals with the Intel compiler (ICC) but the general technical discussion is valid for other compilers such as gcc and llvm
==== Inline Assembly Language ====
* [[Inline Assembly Language]]
* [http://developer.arm.com ARM Developer Information Centre]
** [https://developer.arm.com/products/architecture/a-profile/docs/den0024/a ARM Cortex-A Series Programmer’s Guide for ARMv8-A]
* The ''short'' guide to the ARMv8 instruction set: [https://www.element14.com/community/servlet/JiveServlet/previewBody/41836-102-1-229511/ARM.Reference_Manual.pdf ARMv8 Instruction Set Overview] ("ARM ISA Overview")
* The ''long'' guide to the ARMv8 instruction set: [https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile] ("ARM ARM")
==== C Intrinsics - AArch64 SIMD ====
* [https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics ARM NEON Intrinsics Reference]
* [https://gcc.gnu.org/onlinedocs/gcc/ARM-C-Language-Extensions-_0028ACLE_0029.html GCC ARM C Language Extensions]
=== Week 5 Deliverables ===
* Blog about the SIMD Lab
== Week 6 ==
=== Week 6 - Class I ===
* [[Compiler Optimizations]]
* Advanced Compiler Optimizations
** [[Profile Guided Optimization]]
** [[Link Time Optimization]]
* [[Profiling]]
=== Week 6 - Class II ===
* Continue work on the [[SPO600 SIMD Lab|SIMD Lab]] (Lab 5)
=== Week 6 Deliverables ===
* Blog about your results to Lab 5
== Week 7 ==
=== Week 7 - Class I ===
Building software...
* Configuration Systems
** make-based systems
*** [https://www.gnu.org/software/automake/manual/html_node/index.html The GNU Build System: autotools, autoconf, automake]
**** GNU autotools makes extensive use of the ''configuration name'' ("triplet") -- ''cpu-manufacturer-operatingSystem'' or ''cpu-manufacturer-kernel-operatingSystem'' (e.g.,
**** config.guess and config.sub
*** CMake
*** qmake
*** Meson
*** iMake and Others
** Non-make-based systems
*** Apache Ant
*** Apache Maven
*** Qt Build System
* Building in the Source Tree vs. Building in a Parallel Tree
** Pros and Cons
** [https://www.gnu.org/software/automake/manual/html_node/VPATH-Builds.html#VPATH-Builds GNU automake ''vpath'' builds]
* Installing and Testing in non-system directories
** Configuring installation to a non-standard directory
*** Running <code>configure</code> with <code>--prefix</code>
*** Running <code>make install</code> as a non-root user
*** DESTDIR variable for <code>make install</code>
** Runtime environment variables:
*** PATH
*** LD_LIBRARY_PATH and LD_PRELOAD (see the [http://man7.org/linux/man-pages/man8/ld.so.8.html ld.so manpage])
** Security when running software
*** Device access
**** Opening a TCP/IP or UDP/IP port below 1024
**** Accessing a <code>/dev</code> device entry
***** Root permission
***** Group permission
*** SELinux Type Enforcement
**** Enforcement mode
***** View enforcement mode: <code>getenforce</code>
***** Set enforcement mode: <code>setenforce</code>
**** Changing policy
***** [https://fedoraproject.org/wiki/SELinux/audit2why audit2why]
***** [https://fedoraproject.org/wiki/SELinux/audit2why audit2allow]
* Build Dependencies
* Packaging
* General information about the SPO600 projects
** Goal
** Stages
** Approaching the Project
=== Week 7 - Class II ===
* [[Fall 2019 SPO600 Project|Project Selection]]
=== Week 7 Deliverables ===
* Catch up on any incomplete labs (and blog about them)
* Blog about your project selection progress
== Week 8 ==
=== Week 8 - Class I ===
==== Overview/Review of Processor Operation ====
* Fetch-decode-dispatch-execute cycle
* Pipelining
* Branch Prediction
* In-order vs. Out-of-order execution
** Micro-ops
==== Memory Basics ====
* Organization of Memory
** Process organization
*** Text, data
*** Stack
*** Heap
** System organization
*** Kernel memory in process maps
*** Use of unallocated memory for buffers and cache
* Memory Speeds
* Cache
** Cache lookup
** Cache synchronization and invalidation
** Cache line size
* Prefetch
** Prefetch hinting
==== Memory Architecture ====
* Virtual Memory and Memory Management Units (MMUs)
** General principles of Virtual Memory and operation of MMUs
** Memory protection
*** Unmapped Regions
*** Write Protection
*** Execute Protection
*** Privilege Levels
** Swapping
** Text sharing
** Demand Loading
** Data sharing
*** Shared memory for Inter-Process Communication
*** Copy-on-Write (CoW)
** Memory mapped files
==== Memory Statistics ====
* Resident Set Size (RSS) and Virtual Set Size (VSS)
* Total memory consumption per process
* Total system memory consumption
==== Software Impact ====
* Alignment checks
* Page boundary crossing
=== Week 8 - Class II ===
* Project Discussion
=== Week 8 Deliverables ===
* Blog about your project work
<!--
=== Week 5 - Class II ===
* SIMD and Auto-vectorization
* [[Inline Assembly Language|Inline Assembler]]* C Intrinsics
* [[SPO600 Vectorization Lab|Vectorization Lab]] (Optional lab - recommended)
* Organization of Memory
** Process organization
*** Text, data
*** Stack
*** Heap
** System organization
* Memory Speeds
* Cache
* Virtual Memory and Memory Management Units (MMUs)
** General principles of VM Virtual Memory and operation of MMUs
** Memory protection
*** Unmapped Regions
** Swapping
** Text sharing
** Demand Loading
** Data sharing
*** Shared memory for Inter-Process Communication*** Copy-on-Write (CoW)** Demand Loading
** Memory mapped files
