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→‎Roof-line Analysis
= Intel Advisor =
Intel Advisor is a set of design and analysis tool for optimizing performance. This is done by using the Advisor tools used that will help to measure analyze and improve threading, vectorization, and memory use within the performance of an application. They Advisor supports C, C++, Fortran, Python, and OpenMP. The Tools highlighted in this wiki page are Vectorization advisorthe survey analysis, Rooflinedependencies analysis, Threadingroof-line analysis, Off loadingand memory access pattern analysis. Survey Analysis will identify points in your code where vectorization or parallelization is possible and improvement to make the execution faster. Dependencies Analysis will identify data Dependencies in your code. Roofline Analysis will find performance headroom against hardware limitations and get insights for an effective optimization roadmap. Memory Access Pattern Analysis can check for various memory issues, such as non-contiguous memory accesses and flow Graphunit strides.
== Group Members ==
[mailto:asothilingam1@myseneca.ca?subject=SB Anojan Sothilingam]
= Intel Survey Analysis =
A Survey analysis will create a Survey Report that outlines instances:
• Provide general performance issue
 
== How to set up a Survey Analysis ==
Microsoft Visual Studio Integration
 
1. From the Tools menu, choose Intel Advisor > Start Survey Analysis
 
[[File:Intel_advisor.png|1000px]]
 
Intel Advisor GUI
 
1. Select new project
 
[[File:Intel-Advisor-GUI-1.png|1000px]]
 
2. Enter the project name and select Create Project
 
[[File:Intel-Advisor-GUI-2.png|1000px]]
 
3. Find and Select the executable file of your program and press OK
 
[[File:Intel-Advisor-GUI-3.png|1000px]]
 
4. Select the collect button below Survey Target
 
[[File:Intel-Advisor-GUI-4.png|1000px]]
 
[[File:Intel-Advisor-GUI-5.png|1000px]]
== Code Example ==
</source>
= Dependencies Analysis =The compiler will be unable to vectorize loops if there are potential data dependencies. The dependencies analysis will create a dependencies report that shows where possible data dependencies exist. The report will also have details about the type of dependency and how to solve the dependency. == How to set up a Survey Dependencies Analysis ==1. [[File:DA_SS1.png|1000px]] [[File:DA_SS2.png|1000px]] = Roof-line Analysis =The roofline tool creates a tool line model, to represent an application's performance in relation to hardware limitations, including memory bandwidth and computational peaks. To measure performance we use 2 axes with GFLOPs (Giga Floating point operations per second) on the y-axis, and AI(Arithmetic Intensity(FLOPs/Byte)) on the x-axis both in log scale, with this we can begin to build our roof-line. Now for any given machine, its CPU can only perform so many FLOPs so we can plot the CPU cap on our chart to represent this. Like the CPU a memory system can only supply so many gigabytes, we can represent this by a diagonal line(N GB/s * X FLOPs/Byte = Y GFLOPs/s). (pic) This chart represents the machine's hardware limitation, and it's best performance at a given AI Every function, or loop, will have specific AI, when ran we can record its GFLOPs, Because we know Its AI won't change and any optimization we do will only change the performance, this is useful when we want to measure the performance of a given change or optimization.  [[File:Flops.PNG]] = How to set up a Roof-line Analysis =
Microsoft Visual Studio Integration
1. select project [[File:Intel_advisorStep_1.1.PNG]] 2. Go to Intel advisor and select roof-line tool [[File:Step_2.png|1000px]] 3. let roof-line tool analyze data
Intel Advisor GUI [[File:Step_3.PNG]]
[[File:Intel-Advisor-GUI-14.png|1000px]]review data
[[File:Intel-Advisor-GUI-2Step_4.png|1000pxPNG]]
[[File:Intel= Memory Access Pattern Analysis =We can use the MAP analysis tool to check for various memory issues, such as non-Advisor-GUI-3contiguous memory accesses and unit strides. Also we can get information about types of memory access in selected loops/functions, how you traverse your data, and how it affects your vector efficiency and cache bandwidth usage.png|1000px]]
[[File:Intel= How to set up Memory Access Pattern Analysis =step 1 run roof-Advisor-GUI-4.png|1000px]]line tools
[[File:Intel-Advisor-GUI-5Step_4.png|1000pxPNG]]
= Intel Roof-line Analysis =The roofline Step 2 run Map tool creates a tool line model, to represent an application's performance in relation to hardware limitations, including memory bandwidth and computational peaks. To measure performance we use 2 axes with GFLOPs (Giga Flops/sec) on the y-axis, and AI(Arithmetic Intensity(FLOPs/Byte)) on the x-axis both in log scale, with this we can begin to build our roof-line. Now for any given machine, its CPU can only perform so many FLOPs so we can plot the CPU cap on our chart to represent this. Like the CPU a memory system can only supply so many gigabytes, we can represent this by a diagonal line(N GB/s * X FLOPs/Byte = Y GFLOPs/s). (pic) This chart represents the machine's hardware limitation, and it's best performance at a given AI
Every function, or loop, will have specific AI, when ran we can record its GFLOPs Because we know Its AI won't change and any optimization we do will only change the performance, this is useful when we want to measure the performance of a given change or optimization[[File:Step_5.PNG]]
Step 3 Review data
[[File:FlopsStep_6.PNG]]
<source>#include <iostream>/* Copyright (C) 2010-2017 Intel Corporation. All Rights Reserved. * * The source code, information and material ("Material") * contained herein is owned by Intel Corporation or its * suppliers or licensors, and title to such Material remains #include <iomanip> * with Intel Corporation or its suppliers or licensors.#include <cstdlib> * The Material contains proprietary information of Intel or #include <chrono> * its suppliers and licensors. The Material is protected by #include <omp * worldwide copyright laws and treaty provisions.h>using namespace std::chrono; * No part of the Material may be used, copied, reproduced, * modified, published, uploaded, posted, transmitted, distributed #define NUM_THREADS 1 * or disclosed in any way without Intel's prior express written // report system time * permission. No license under any patent, copyright or other// * intellectual property rights in the Material is granted to or void reportTime(const char * msgconferred upon you, either expressly, steady_clock::duration span) {by implication, inducement, * estoppel or otherwise. Any license under such intellectual * property rights must be express and approved by Intel in writing. * Third Party trademarks are the property of their respective owners. auto ms = duration_cast<milliseconds>(span); * Unless otherwise agreed by Intel in writing, you may not remove std::cout << msg << " - took - " << * or alter this notice or any other notice embedded in Materials ms * by Intel or Intel's suppliers or licensors in any way.count() << * This file is intended for use with the " millisecondsMemory Access 101" tutorial. */ #include <iostream> #include < time.h>using namespace std::endl;}
const int main(int argc, char** argv) { if (argc !LOOPS = 2) { std::cerr << argv[0] << ": invalid number of arguments\n"1500000; std::cerr << "Usage: " << argv[0] << " no_of_slices\n"; return 1; } const int n SIZE = std::atoi(argv[1])14992; const int* t; steady_clock::time_point ts, teSTEPS = SIZE / 2;
// calculate pi by integrating the area under 1/(1 + x^2) in n steps ts = steady_clock::now(); int mt = omp_get_num_threads(), nthreadsfloat floatArray[SIZE]; double pi; double stepSize = 1.0 / (double)n; omp_set_num_threads(NUM_THREADS); t = new intdoubleArray[3SIZE]; #pragma omp parallel { int i, tid, nt; double x, sum; tid = omp_get_thread_num(); nt = omp_get_num_threads(); if (tid == 0) nthreads = nt; for ( i = tid, sum=0.0; i<n; i+=nt) { x = ((double)i + 0.5) * stepSize; sum += 1.0 / (1.0 + x * x); } #pragma omp critical pi += 4.0 * sum * stepSize; }
te = steady_clock::now()time_t start;time_t finish;
std::cout int main(){ // Contiguous data access, same number of iterations as the noncontiguous. start = time(NULL); #pragma nounroll for (float i = 0; i <LOOPS; i++) { #pragma nounroll for (int j = 0; j < "n STEPS; j += 1) { floatArray[j] = " << n <<" " << nthreads <<i; } } std::fixed << std::setprecision finish = time(15NULL) ; cout << "\n pi(exact) = Contiguous Float: " << 3.141592653589793 finish - start << "\n pi(calcd) = " << pi << std::endl; reportTime("Integration", te - ts);}
// Contiguous data access on doubles, so that it should require roughly
// the same number of cache line loads as the 2-stride float loop.
start = time(NULL);
#pragma nounroll
for (double i = 0; i < LOOPS; i++)
{
#pragma nounroll
for (int j = 0; j < STEPS; j += 1)
{
doubleArray[j] = i;
}
}
finish = time(NULL);
cout << "Contiguous Double: " << finish - start << "\n";
// Stride-2 float. Same number of iterations as the contiguous version, // same number of cache line loads as the double loop. Slower than both. start = time(NULL); #pragma nounroll for (float i = 0; i < LOOPS; i++) { #pragma nounroll for (int j = 0; j < STEPS * 2; j += 2) { floatArray[j] = i; } } finish = time(NULL); cout << "Noncontiguous Float: " << finish - start </source>< "\n";
= Intel Memory Access Pattern Analysis = return EXIT_SUCCESS;We can use the MAP analysis tool to check for various memory issues, such as non-contiguous memory accesses and unit strides.}
= Intel Dependencies Analysis =The compiler will be unable to vectorize loops if there are potential data dependencies. The dependencies analysis will create a dependencies report that shows where possible data dependencies exist. The report will also have details about the type of dependency and how to solve the dependency.</source>
== Sources ==
https://www.youtube.com/watch?v=h2QEM1HpFgg - Roofline Analysis in Intel Advisor tutorial
https://software.intel.com/content/www/us/en/develop/documentation/advisor-user-guide/top/survey-trip-counts-flops-and-roofline-analyses/survey-analysis.html
 
https://techdecoded.intel.io/quickhits/advantages-of-vectorization-and-the-effects-of-data-size/#gs.mgu8q9
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